ZTPU: fixed-point hardware in ZLang HDL
A source-available accelerator design and cycle-level MicroGPT simulation demo, with separate licensing and documented limits.
Queued engines for the compute path
ZTPU is written in ZLang HDL. Its matrix, vector and Adam engines share a unified buffer and accept queued commands. The public integration modules expose configuration, memory interfaces, completions, interrupts and counters.
The reference arithmetic is Q16. Experimental lower-precision modes have separate restrictions. Fixed-point rounding and lookup-table approximations differ from the original floating-point model.
Inspect the integration source ↗| Operation | Hardware path |
|---|---|
| Linear projections and attention products | Matrix engine (MXU) |
| RMSNorm, softmax, ReLU and residual arithmetic | Vector engine (VMU) |
| Adam parameter updates | Adam engine |
| Tensor and KV-cache movement | Unified buffer, layout engine and AXI DMA |
The MicroGPT demonstration
The demonstration follows Andrej Karpathy's MicroGPT. Host code prepares character tokens and a floating-point checkpoint, quantizes weights, moves tensors, and samples generated names. Inference uses the queued Q16 matrix and vector engines in the native hardware simulator.
This is cycle-level simulation, not real-time inference or a silicon benchmark. The first compilation and a sampling run can take substantial time. Generated probabilities and names differ from the floating-point reference.
Use the project's own toolchain pin
The ZTPU README at this snapshot specifies Python 3.12 and compiler revision 85138c88bb81, with its matching Linux x86-64 simulation wheel. That pin is separate from this website's Counter/documentation snapshot. Follow the complete setup in the project README before running its commands.
Licensing and validation boundaries
ZTPU uses PolyForm Noncommercial 1.0.0; commercial terms are separate. Its licensing is distinct from the Apache-2.0 Community compiler. Read the project's license and published source/validation notes for the configuration you intend to use.
Published validation applies to the stated configurations and checks. Target synthesis, physical timing and silicon measurements are separate stages. The website serves project information and illustration; it does not execute hardware jobs.
Inspect the design.
Read the pinned source or discuss a hardware workflow with the project.