Clocked state and timing

Start with one clock domain

The Counter declares clock clk and reset rst. In this single-domain module, the register belongs to that clock without an annotation. Synchronous active-high reset is the default in the pinned language reference.

Current values and next-state actions

y = count is a combinational read of current state. count <- truncate(count + 1) describes a next-state action. It does not change count partway through an expression as a software assignment might.

The emitted Counter RTL has a rising-edge clocked block. If reset is asserted at that edge, the reset branch takes effect. Otherwise the register stores its next value. Read the recorded source-to-RTL walkthrough to inspect the actual output.

Cycle behavior is not timing closure

A cycle-level event schedule lets you inspect state changes and output values. It does not establish setup or hold margins, placement, routing or maximum clock frequency. Those depend on the target implementation and physical timing analysis.

Multiple domains need explicit ownership

Independent clocks have their own reset contracts and state ownership. The compiler rejects implicit clock-domain crossing; an unannotated local does not make a crossing safe. Supported crossings and adapters are restricted to the documented profiles.

See sequential state and storage, the physical clock/reset contract, and hierarchy and protocols for exact supported forms.

Inspect the waveform

Use the Counter event schedule and native simulation command in Get started. Compare the clock and reset events with the register output. Keep the source revision, event schedule and tool version together when reporting a result.