ZLANG HDL / GUIDES/COUNTER-TO-SYSTEMVERILOG

From Counter to SystemVerilog

Read the source, the compiler check and the generated RTL, one step at a time.

ZLang HDL documentationPublished 2026-11-09Source c768da0bce8b ↗

What the Counter declares

The module declares one clock and one reset. count is an eight-bit unsigned register with reset value zero. The output y reads its current value. The final line describes the next value to store.

Adding one widens the arithmetic result. truncate explicitly converts that result back to the eight-bit destination. When the counter reaches 255, its next stored value wraps to zero.

Recorded compiler exampleZLang 0.1.0a24Source c768da0bce8b ↗

ZLang source

Public source

examples/counter.zhl

module Counter {
    clock clk
    reset rst

    reg count : u8 = 0
    out y     : u8

    y = count
    count <- truncate(count + 1)
}

The original example, unchanged from the linked revision.

Compiler check

Recorded output

zlang examples/counter.zhl --top Counter --check

zlang: ok: examples/counter.zhl (top Counter; syntax and semantics valid)

Recorded process exit status: 0. Syntax and semantic checking only.

Generated SystemVerilog

Recorded output

zlang examples/counter.zhl --top Counter --systemverilog build/Counter.sv

`default_nettype none
module Counter (
  input wire logic clk,
  input wire logic rst,
  output logic [7:0] y
);
  // Generated from backend-independent typed ZLang IR.
  logic [7:0] count;
  always_ff @(posedge clk) begin
    if (rst) begin
      count <= 8'd0;
    end else begin
      count <= 8'(({{1{1'b0}}, count} + 9'd1));
    end
  end
  assign y = count;
endmodule
`default_nettype wire

Recorded process exit status: 0. Output file: build/Counter.sv.

This is a recorded example, not a live compiler. Semantic checking and RTL generation do not establish synthesis results, timing closure, or a formal proof.

Reproduce these commands

zlang examples/counter.zhl --top Counter --check
zlang examples/counter.zhl --top Counter --systemverilog build/Counter.sv

Compiler 0.1.0a24 · Python 3.12.3 · Lark 1.3.1 · egglog 14.0.0. Use the linked source revision and its installation instructions.

Read the compiler result separately from the RTL

The check transcript records a successful syntax and semantic check at compiler revision c768da0bce8b. It confirms that this source passed that compiler's checks. It is not a proof that every possible hardware property holds.

The generated always_ff block updates the register on the rising clock edge. The reset branch loads zero; the other branch stores the truncated sum. The continuous assignment exposes the current register value as y.

Try it locally

Follow Get started for the pinned toolchain and the checked-in event schedule. The website serves recorded files; it does not compile designs or run a simulator.

Pinned checkout commands

zlang examples/counter.zhl --top Counter --check
zlang examples/counter.zhl --top Counter --systemverilog build/Counter.sv

What to check next

Simulation exercises the event schedule you supply. Formal results apply to the stated properties and bounds. Synthesis, place and route, and timing analysis require the relevant target tools. A clean compiler check does not replace these steps.

Continue with clocked state and timing, or inspect the larger public examples.

Keep exploring

PRACTICAL GUIDE

Canonical manuals and PDFs →